1. Field of the Invention
The present invention is related to a reconfigurable integrated circuit, and more specifically related to a system for configuring an integrated circuit and a configuring method thereof to suppress reduction of performance yield due to process variation of semiconductors.
2. Discussion of the Background
In recent years, due to miniaturization of the semiconductor process, variation in the device characteristic in chips increases, and reduction in the performance yield becomes a problem. The performance yield is the number of chips capable of meeting the required performance divided by the number of chips produced. As for variation between chips (or variation having correlation over a wide range) it is effective to perform a correction after chip fabrication by controlling the threshold voltage of transistors by controlling the back bias, as described in the Non-Patent Document 1 and the Patent Document 1, 2. However, when uncorrelated variation occurs between chips, especially between transistors, it is necessary to reduce the granularity of bias control, which leads to a problem of increasing the circuit overhead.
On the other hand, a different approach can be taken to the reconfigurable integrated circuit such as FPGAs (field-programmable gate array), wherein the circuit function can be changed as many times as needed after fabricating chips.
FIG. 1 shows a typical example of a structure of a reconfigurable integrated circuit, and FIG. 1(a) shows a tile of the reconfigurable integrated circuit and FIG. 1(b) shows a tile array thereof.
The reconfigurable integrated circuit is typically constructed such that a tile 1 containing a programmable switch matrix 3 and a functional block 2 is arranged as a tile array 6 shown in FIG. 1, and tiles are connected by a vertical and horizontal interconnection channels 5, 4, respectively.
In other words, the reconfigurable integrated circuit is composed of regularly arranged programmable functional blocks and programmable interconnecting network connecting the functional blocks mutually. The interconnecting network and the functional blocks can change their connection topologies and functions by a configuring memory.
As a configuring memory, a volatile memory such as a SRAM (static random access memory) and a DRAM (dynamic random access memory) and a non-volatile memory such as a flash EEPROM (electronically erasable and programmable read only memory), a MRAM (magnetic random access memory) and a FeRAM (ferroelectric random access memory) can be used, and a configuring memory utilizing a SRAM or a flash EEPROM is currently most used.
Generally a user describes a required function using a function description language such as a HDL (Hardware description language) or a programming language, generates information to determine a function of the reconfigurable integrated circuit using a mapping tool (or a compiler), and loads the information into a configuring memory of the reconfigurable integrated circuit, thereby realizing a desired function on the reconfigurable integrated circuit. Besides, a process of assigning the function described by the user to a plurality of functional blocks of the reconfigurable integrated circuit is referred to as a mapping, and a tool to perform the process automatically is referred to as a mapping tool.
Among the reconfigurable integrated circuits, there are a fine-grain reconfigurable integrated circuit such as a FPGA which can change the circuit configuration as a unit of a gate, a coarse-grain reconfigurable integrated circuit which can change the circuit configuration as a unit of ALU (arithmetic logic unit) or a multiplier, and their mixture reconfigurable integrated circuit. A dynamic reconfigurable integrated circuit which includes a plurality of configuring memories capable of instantaneous switching and realizes a plurality of circuit functions in time division manner on a single reconfigurable integrated circuit by switching over the configuring memories is also a kind of the reconfigurable integrated circuit.
One of the easiest configuring methods of avoiding variation in such reconfigurable integrated circuits is a method that variation is measured in advance and a circuit element having good characteristics is assigned to the most critical part determining the performance of the circuit. Important things to realize the method of avoiding the variation in such a reconfigurable integrated circuit are diagnosis of variation in each chip (to examine what characteristic each circuit element has) and mapping by taking the variation into account.
The diagnosis of variation of the reconfigurable integrated circuit can be performed by configuring a measurement circuit for device characteristics such as a ring oscillator on the reconfigurable integrated circuit. However, this method takes long time to evaluate variation in fine-grain and has difficulty of corresponding to the uncorrelated variation in transistors.
Although it is considered possible to evaluate variation more quickly by integrating a circuit for evaluating variation in advance into a reconfigurable integrated circuit, the diagnosis of variation in fine-grain is still difficult because of large circuit overhead and variation in the detection circuit itself.
The difficulty in failure diagnosis has been conventionally considered one of the factors to increase cost because the number of possible circuit states is extremely large in the reconfigurable integrated circuit. The diagnosis of variation is a still more difficult problem because it requires detecting analog values instead of digital values as in the failure diagnosis. Therefore the addition of the diagnosis of variation to the fabrication process of the reconfigurable integrated circuit results in a large increase in cost.
Also, besides the problem that performing a mapping separately on the respective chip takes an extremely long time to fabricate a product mounting the chip, there exists another problem of the stability of an automatic mapping tool. It is difficult for the algorithm of the automatic mapping tool to give stably an optimal solution. Performing a mapping separately on the respective chip results in reduction of performance since an increase in performance margin is required by taking the instability of solution into account.
[Patent document 1]Japanese Patent Application 2000-286387.
[Patent document 2]Japanese Patent Application 2004-20325.
[Non-Patent document 1]D. R. Ditzel, “Power Reduction using LongRun2 in Transmeta's Efficieon Processor” Spring Processor Forum Presentation, 2006.
The purpose of the present invention is to provide a system for configuring an integrated circuit and a configuring method thereof of the reconfigurable integrated circuit which do not need circuit overhead for variation correction and diagnosis of variation.